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2024-05-18 - 19:57

Dates and Events:

OSADL Articles:

2023-11-12 12:00

Open Source License Obligations Checklists even better now

Import the checklists to other tools, create context diffs and merged lists


2023-03-01 12:00

Embedded Linux distributions

Results of the online "wish list"


2022-01-13 12:00

Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completed

Another important milestone on the way to interoperable Open Source real-time Ethernet has been reached


2021-02-09 12:00

Open Source OPC UA PubSub over TSN project phase #3 launched

Letter of Intent with call for participation is now available



OSADL Projects

OSADL QA Farm on Real-time of Mainline Linux

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Number of cores/hyperthreads and bogoMIPS (x86 CPU strings, Intel names)

Box ↑ArchCoresMHzBogo​MIPSEffective
r0s0x86_​644 x 22,50040,00018.05. 13:10
r0s1x86_​644 x 22,30055,99218.05. 13:11
r0s1sx86_​644 x 23,30052,67218.05. 13:12
r0s2x86_​644 x 23,50055,86418.05. 13:14
r0s2sx86_​6410 x 13,70073,99018.05. 13:16
r0s3x86_​648 x 23,600115,20018.05. 13:17
r0s3sx86_​644 x 23,60067,20018.05. 13:22
r0s4x86_​648 x 23,600115,20018.05. 13:23
r0s4sx86_​648 x 23,600115,20018.05. 13:25
r0s5x86_​648 x 23,500115,20018.05. 13:27
r0s5sx86_​648 x 23,600115,20018.05. 13:29
r0s6x86_​648 x 23,600115,20018.05. 13:35
r0s6sx86_​6410 x 23,700147,98018.05. 13:36
r0s7x86_​648 x 23,600115,20018.05. 13:39
r0s7sx86_​642 x 23,70029,52818.05. 13:44
r0s8x86_​648 x 23,600115,20018.05. 13:46
r0s8sx86_​646 x 23,47083,38818.05. 13:48
r1s0x86_​644 x 13,10024,79618.05. 13:50
r1s1x86_​642 x 22,60021,69618.05. 13:51
r1s2x86_​644 x 12,30028,00018.05. 13:52
r1s2sx86_​644 x 12,30028,00018.05. 13:54
r1s3x86_​644 x 12,80022,42418.05. 13:57
r1s3sx86_​644 x 12,60020,88826.10. 13:42
r1s4arm​v7l2 x 11,2004818.05. 13:59
r1s4sarm​v7l2 x 14004818.05. 14:00
r1s5aarch​644 x 11,20079618.05. 14:01
r1s6x86_​642 x 22,13017,06418.05. 14:01
r1s6sx86_​642 x 21,66713,33218.05. 14:03
r1s7arm​v6l1 x 11,66753018.05. 14:05
r1s8i6861 x 21,6006,39818.05. 14:06
r1s8sx86_​644 x 11,90015,19618.05. 14:07
r2s0x86_​644 x 13,10024,80018.05. 14:08
r2s1arm​v5tejl1 x 120019918.05. 14:10
r2s2arm​v7l1 x 172049918.05. 14:14
r2s3arm​v7l0 x 1 x 162462418.05. 14:15
r2s3sarm​v7l0 x 1 x 16001,20018.05. 14:16
r2s4mips​641 x 180053124.12. 13:46
r2s5ppc1 x 13966627.03. 13:43
r2s6i6861 x 11,5002,99918.05. 14:18
r2s6saarch​644 x 11,3506418.05. 14:20
r2s7aarch​644 x 12,40043218.05. 14:20
r2s7saarch​644 x 11,50043218.05. 14:23
r2s8ppc1 x 14006618.05. 14:25
r3s0i6864 x 23,50055,99218.05. 14:26
r3s1i6864 x 12,40019,12718.05. 14:28
r3s2riscv641 x 11,00028418.05. 14:29
r3s2sriscv644 x 1028418.05. 14:31
r3s3x86_​646 x 23,33379,99218.05. 14:32
r3s4aarch​646 x 11,3009618.05. 14:34
r3s5i5861 x 113326518.05. 14:38
r3s5sppc2 x 11,20040018.05. 14:42
r3s6x86_​641 x 11,6603,33318.05. 14:43
r3s6sx86_​642 x 22,66721,33218.05. 14:45
r3s7i6861 x 15331,06618.05. 14:46
r3s8i6866 x 13,20038,52618.05. 14:47
r4s0x86_​642 x 22,30018,39618.05. 14:49
r4s1arm​v7l4 x 11,5001,08018.05. 14:50
r4s1sarm​v7l4 x 11,5001,08018.05. 14:52
r4s2arm​v7l1 x 180079618.05. 14:55
r4s2sarm​v7l1 x 180053018.05. 14:57
r4s3i5861 x 150099618.05. 15:01
r4s3si6861 x 11,4662,93218.05. 15:03
r4s4ppc4 x 11,20049818.05. 15:05
r4s5arm​v7l1 x 1500018.05. 15:08
r4s5saarch​644 x 11,60020027.03. 14:13
r4s6x86_​644 x 23,40054,25618.05. 15:09
r4s6sarm​v7l0 x 1 x 11,0006618.05. 15:13
r4s7i6864 x 11,83314,66418.05. 15:16
r4s7sx86_​642 x 11,8337,33218.05. 15:17
r4s8arm​v7l1 x 140039818.05. 15:19
r4s8sarm​v7l1 x 140039818.05. 15:20
r5s0x86_​642 x 22,20017,58218.05. 15:21
r5s1x86_​646 x 13,33340,09218.05. 15:22
r5s2x86_​644 x 12,70021,69918.05. 15:24
r5s2sx86_​644 x 24,00063,86312.04. 01:34
r5s3x86_​644 x 22,00031,87218.05. 15:25
r5s3sx86_​644 x 11,60012,74818.05. 15:27
r5s4x86_​642 x 22,53020,26418.05. 15:29
r5s4sx86_​642 x 22,53020,26418.05. 15:31
r5s5arm​v7l1 x 160059718.05. 15:34
r5s5sarm​v7l1 x 160060018.05. 15:37
r5s6ppc1 x 153313318.05. 15:42
r5s7arm​v7l1 x 15286418.05. 15:43
r5s7sarm​v7l1 x 15286418.05. 15:46
r6s0x86_​642 x 10 x 21,700136,18018.05. 15:48
r6s1x86_​642 x 12,0007,97818.05. 15:50
r6s2x86_​642 x 11,6679,57818.05. 15:52
r6s3x86_​644 x 22,20035,12018.05. 15:53
r6s4x86_​642 x 11,1004,37618.05. 15:55
r6s5i6861 x 11,5002,99218.05. 15:57
r6s6i6861 x 11,6003,19118.05. 15:59
r6s7i6862 x 12,3009,17611.01. 02:44
r6s8x86_​642 x 22,30018,35618.05. 16:01
r7s0x86_​642 x 22,30018,40018.05. 16:02
r7s1x86_​644 x 11,60012,84018.05. 16:03
r7s2sarm​v7l4 x 11,50072013.07. 02:16
r7s3arm​v6l1 x 1700518.05. 16:05
r7s3sarm​v7l4 x 11,40015218.05. 16:08
r7s4arm​v7l1 x 153634818.05. 16:11
r7s4sarm​v7l4 x 11,5001,08018.05. 16:12
r7s5i6861 x 11,3002,59318.05. 16:14
r7s6arm​v7l1 x 11,00039828.02. 14:10
r7s7x86_​644 x 11,60012,76718.05. 16:15
r7s7sx86_​642 x 22,30018,39618.05. 16:16
r7s8arm​v7l1 x 11,00099518.05. 16:18
r7s8sarm​v7l1 x 11,00099618.05. 16:20
r8s0x86_​642 x 22,30018,40018.05. 16:20
r8s1i5861 x 135070118.05. 16:22
r8s2x86_​642 x 22,10016,76018.05. 16:23
r8s2sx86_​642 x 22,10016,76018.05. 16:25
r8s3x86_​644 x 12,66721,28018.05. 16:27
r8s4x86_​644 x 21,60028,80018.05. 16:28
r8s4sx86_​644 x 21,60028,80018.05. 16:30
r8s5i6864 x 23,40054,40018.05. 16:31
r8s6arm​v7l1 x 150049818.05. 16:33
r8s7x86_​642 x 12,70010,77618.05. 16:34
r8s7sx86_​642 x 13,30013,19818.05. 16:36
r8s8x86_​642 x 11,3005,14418.05. 16:37
r9s0x86_​642 x 22,30018,40018.05. 16:39
r9s1x86_​642 x 12,0003,99218.05. 16:40
r9s1sarm​v7l1 x 101,25014.04. 18:03
r9s2x86_​644 x 11,60012,74818.05. 16:41
r9s2sx86_​644 x 11,60012,74830.08. 17:02
r9s3x86_​644 x 11,60012,74818.05. 16:43
r9s3sx86_​644 x 13,00024,00018.05. 16:44
r9s4i6861 x 21,0003,99018.05. 16:46
r9s4sx86_​642 x 11,3335,34718.05. 16:52
r9s5x86_​642 x 12,70010,77413.07. 03:15
r9s5sx86_​642 x 13,50013,99818.05. 16:54
r9s6x86_​642 x 23,00023,94418.05. 16:56
r9s7arm​v7l2 x 11,000017.05. 17:06
r9s8sarm​v7l1 x 180079618.05. 16:58
ras0x86_​642 x 22,30018,41618.05. 16:59
ras1i6861 x 11,4002,79918.05. 17:00
ras2x86_​642 x 11,0674,26618.05. 17:01
ras3aarch​648 x 12,0004,00018.05. 17:02
ras3sarm​v7l1 x 11,30084018.05. 17:03
ras4arm​v7l1 x 150039818.05. 17:04
ras4sarm​v7l1 x 160059707.02. 02:45
ras5arm​v7l2 x 11,0002418.05. 17:05
ras5sarm​v7l2 x 11,0002418.05. 17:06
ras6aarch​648 x 12,0003,20018.05. 17:06
ras6sarm​v7l1 x 11,0001,98718.05. 17:08
ras7ppc1 x 13966518.05. 17:09
ras8x86_​644 x 11,60014,40018.05. 17:09
ras8sx86_​644 x 11,60012,74818.05. 17:11
rbs0i6862 x 22,50017,60018.05. 17:13
rbs1x86_​644 x 12,00015,97218.05. 17:14
rbs2x86_​644 x 12,00015,97218.05. 17:15
rbs2sx86_​641 x 13,500007.09. 15:06
rbs3arm​v7l4 x 19962818.05. 17:16
rbs3sarm​v7l4 x 11,40035618.05. 17:17
rbs4x86_​644 x 11,2009,60018.05. 17:19
rbs4sx86_​644 x 11,60012,74818.05. 17:21
rbs5i6864 x 2049,53918.05. 17:23
rbs5saarch​644 x 11,6006418.05. 17:23
rbs6x86_​644 x 11,91515,32418.05. 17:24
rbs6sx86_​642 x 11,3335,33218.05. 17:26
rbs7arm​v7l4 x 19962818.05. 17:27
rbs7sarm​v7l4 x 19962418.05. 17:29
rbs8arm​v7l2 x 16662,65018.05. 17:31
rbs8sx86_​644 x 22,40038,70417.05. 17:45
rcs0x86_​648 x 22,40076,60018.05. 17:33
rcs1x86_​646 x 23,46783,37618.05. 17:35
rcs2x86_​642 x 12,80011,23218.05. 17:36
rcs3i6862 x 11,4005,58618.05. 17:37
rcs3sx86_​644 x 23,30052,69618.05. 17:39
rcs4x86_​642 x 11,1004,37618.05. 17:42
rcs4sx86_​644 x 11,1008,75218.05. 17:44
rcs5x86_​642 x 12,80011,19818.05. 17:45
rcs5sx86_​642 x 12,80011,19818.05. 17:48
rcs6x86_​644 x 23,50063,99211.05. 17:51
rcs7x86_​642 x 21,80014,39618.05. 17:49
rcs7sx86_​644 x 11,50011,98018.05. 17:51
rcs8x86_​6416 x 23,700217,15218.05. 17:57
rcs8sx86_​644 x 23,30052,79218.05. 17:59
rds0x86_​644 x 21,80031,99217.05. 18:21
rds1x86_​644 x 11,91015,32418.05. 18:01
rds2x86_​644 x 11,91015,32418.05. 18:02
rds3x86_​644 x 11,91015,32418.05. 18:03
rds4x86_​644 x 11,91015,32418.05. 18:04
rds5x86_​644 x 11,60012,74818.05. 18:06
rds6x86_​644 x 11,60012,74818.05. 18:07
rds7x86_​644 x 11,60012,74818.05. 18:08
rds8x86_​644 x 11,60012,74818.05. 18:09
res0x86_​644 x 21,80031,99218.05. 18:10
res1x86_​644 x 11,60014,40018.05. 18:12
res1sx86_​644 x 11,60014,40018.05. 18:13
res2x86_​644 x 11,60014,40018.05. 18:14
res3x86_​644 x 12,00015,97218.05. 18:15
res3saarch​640 x 1 x 11,0001,60018.05. 18:16
res4x86_​644 x 11,90015,05218.05. 18:18
res4sx86_​644 x 11,90015,05218.05. 18:19
res5x86_​642 x 22,20019,20018.05. 18:20
res5sx86_​642 x 22,20019,20018.05. 18:22
res6x86_​644 x 11,1008,75218.05. 18:23
res6saarch​644 x 101,60018.05. 18:25
res7arm​v7l0 x 1 x 11,0001218.05. 18:26
res7sarm​v7l0 x 1 x 11,0001212.01. 05:12
res8x86_​644 x 11,90015,05218.05. 18:28
res8sx86_​644 x 11,90015,05218.05. 18:29
rfs0x86_​6416 x 22,000128,00018.05. 18:30
rfs1aarch​644 x 11,50043218.05. 18:31
rfs2aarch​644 x 11,50043218.05. 18:32
rfs4arm​v7l1 x 180080018.05. 18:33
rfs4sarm​v7l1 x 180080018.05. 18:39
rfs6arm​v7l1 x 16671,33218.05. 18:46
rfs6sarm​v7l1 x 16671,33218.05. 18:47
 

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